Conventional DRAM ("Dynamic Random Access Memory") and SRAM ("Static Random Access Memory") bit line sense and latch circuitry has been designed to sense small voltage thresholds arising from the use of either very small memory cells in the case of DRAM or very fast sensing in the case of SRAM. These memory cells are noise sensitive, requiring special physical layout precautions that are painstakingly taken to avoid signal errors when sensing the activation of a bit-line-true ("BLT") or bit-line-complementary ("BLC") of the memory cells and accompanying select circuitry. Generally, a memory cell supplies a read signal through the bit line pair. The signal is sensed, amplified, and transferred to a suitable evaluation circuit such as an array column decoder.
But using the sensing amplifier to overcome noise issues has required a timing signal, or in the alternative, has required static power to maintain the sensing amplifier in an active state. Thus, either a complex circuit has been required for an amplifier/timing signal combination, or an additional power requirement to maintain the sensing amplifier in that active state. In either configuration, power consumption is increased for the circuit overall, as well as the heat output of the circuit.
Increased complexity is also undesirable because of a cascading complexity effect for circuit design. For example, parasitic capacitances are created, compounding speed and electronic noise design hurdles. Also, the noise effects have been further compounded combining memory cell structures with high speed logic applications, such as has been present on embedded memory in microprocessor circuits.
Higher operational speeds are also sought with respect to processor operation. One technique to try to achieve this speed has been to embed a discrete memory circuit on a chip with high-speed processor circuits. But placing memory cells adjacent a processor circuit has not necessarily translated to faster data transmission rates.
Thus, a need exists for a simple sensing circuit for a semiconductor memory structure that does not rely on a timing signal to function, yet is noise tolerant. Also needed is a sensing circuit that actively accelerates the logic state transition slew rate of a memory bit line, thus achieving a higher operational speed of the memory structure.